About the Role

• Understanding the high-level specification and requirements of various units of Interconnect products.
• Define the Micro-architecture for an unit
• Develop Verilog RTL logic design for the unit
• Collaborate with verification team on the test plan development for the blocks and verification closure
• Debug functional or performance issues with the RTL using simulation and debug tools
• Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets

• Education BS or MS in Electrical Engineering or Computer Engineering
• Prior RTL design experience is required.
• Prior verification or CAD experience is a plus

Required Experience

• CPU or compute subsystem memory micro-architecture.
• Knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI) is a plus
• Experience with Verilog or VHDL, coupled with design synthesis targeted to achieve specified frequency, power, and area targets
• Processor system knowledge including basic understanding of SoC systems as well as operating system software